@INPROCEEDINGS{8383900, 
author={R. Hesselbarth and F. Wilde and C. Gu and N. Hanley}, 
  booktitle={2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)},  
 title={Large scale RO PUF analysis over slice type, evaluation time and temperature on 28nm Xilinx FPGAs},  
  year={2018}, 
  volume={}, 
  number={}, 
  pages={126-133}, 
  keywords={clocks;field programmable gate arrays;logic  design;oscillators;PUF analysis;secure secret storage;physical  unclonable functions;programmable logic fabric;field programmable gate  arrays;time-to-response;ring oscillator PUFs;RO-PUFs;FPGA array;Xilinx  FPGAs;temperature 60.0 degC;temperature 100.0 degC;size 28.0 nm;Field  programmable gate arrays;Temperature  measurement;Routing;Arrays;Switches;Clocks;Frequency measurement}, 
  doi={10.1109/HST.2018.8383900}, 
  ISSN={}, 
  month={April},}