Embedded systems in many applications usally consist of multiple different chips and are physically accessible. Therefore, they are at risk from attackers with advanced skills in electronics, communication engineering, implementation engineering or hardware attacks. Such attackers can also obtain access to internal interfaces, such as debugging interfaces, or interfaces of integrated memory chip directly. For these reasons, it is essential to target a high level of hardware security from the very beginning while designing such systems. A comprehensive and tailored design approach and the application of specific cryptographic algorithms is required to establish a high hardware security level according to the respectively relevant threats and circumstances. In most cases, the integration of dedicated security chips with specific features and properties into the embedded system is necessary to protect against such modern hardware attacks.
Side channel or fault attacks are a major threat to security devices.
The modern hardware lab at Fraunhofer AISEC offers a wide range of evaluation services for security critical applications and devices.
Side-channel attacks differ fundamentally from conventional attack on cryptographic algorithms. In the latter case, attackers try to solve a complex mathematical problem or try to search the entire key space to break cryptographic systems. By contrast, side channel attacks operate on information caused by the implementation like the runtime, the power consumption or the electro-magnetic emission. An attacker can use this information to gain knowledge about the secrets stored inside the device. With the state-of-the-art measurement equipment of our hardware lab we evaluate the side-channel security of cryptographic devices. We use this experience to design and implement countermeasures which are fitted to a specific target platform.
Physical attacks aim at extracting secret information from an electronic device. Besides the passive side channel analysis, which restrict on observing the environment of the device, there are also active attacks, so called fault attacks, which try to distrub the device in an applicable manner. In combination with knowledge about the working principle of a cryptographic algorithm, the deliberatly inducted faults can be exploited to gather information about the internally used secrect key.
In order to inject faults, various techniques are effective. Common methods are based on driving a device outside its specified operational conditions (supply voltage level, system clock frequency or temperature). Beyond that, there are more complex techniques like e.g. Laser-based Fault Injection. Focused laser light causes a photo-electric effect which enables to induce faults at a very high precision (temporal and local). This gives the attacker more control and enables to perform a wider range of attacks.
In our hardware test lab we have two different laser stations to carry out fault attacks and evaluate the security of specific devices or countermeasures.
From a security point of view IoT presents several unsolved challenges, which are mainly due to a specific set of domain characteristics. Typical IoT devices are expected to have long operational life span, constrained computational resources, battery capacity and monetary budget. Because of such characteristics many of the well established security technologies cannot be directly transferred into the IoT domain. At Fraunhofer AISEC we contribute to this area by exploring novel hardware and software design patterns which aim to increase the resilience of constrained IoT devices against cyber attacks.
Wireless sensor networks can be considered the sensory organs of the Internet of Things. In many applications, sensor data must be considered sensitive and thus be encrypted and authenticated. However, due to the large number of resource constrained sensor nodes, key management is challenging and tedious. Research at Fraunhofer AISEC paves the way for key management solutions, which permit both secure and user-friendly wireless sensor networks.
FPGAs are becoming very attractive platforms for embedded devices due to reconfigurability and fast time-to-market at acceptable costs. Integrating custom designs, even for high security tasks, has never been easier. Yet, untrusted hardware cores from third parties can undermine the system security from the inside. Our thorough reviewing process identifies vulnerabilities in the system architecture and helps fix them at early design stages. The ubiquity of embedded systems also introduces threats from external attackers getting hold of devices for in-depth analysis. Debug interfaces and external memory modules are promising targets to retrieve intellectual property stored in firmware and to enable counterfeiting.
Our solutions for secure boot, firmware encryption, and secure key storage offer advanced protection for devices in the field. On the software level, operating systems and hypervisors try to isolate applications, while micro-controllers try to protect software from unauthorized read-out. Yet, manipulating and observing shared processor resources allows to bypass protection in both cases. Even trusted execution environments (TEEs) are not secure. Our strategies for system-level hardening and our rigorous software testing methods help restore the isolation and protection of security critical applications.
Machine learning and modern statistical methods can be useful in different circumstances where data needs to be analyzed to expose complex statistical dependencies. We use a variety of advanced statistical algorithms to, for example, evaluate large amounts of data in side-channel analyses of cryptographic implementations or to detect anomalies in sensor networks on resource-limited platforms.
PUFs are circuits on silicon chips that exploit manufacturing variations to generate a device unique bitstring that can be used as a secret, to bind cryptographic keys to it, or for identifying the chip.
In particular they can be used in FPGA applications to provide user accessible secure keystorage, without having to rely on manufacturer provided security features, which may be vulnerable to attacks or are not trusted.
Our research includes improved and novel implementations of PUF circuits on FPGAs as well as their integration into FPGA and other embedded systems. An array of over 200 FPGAs allows us to analyze the statistical properties of our PUF implementations.
Searching for data leaks in applications
Researchers of Fraunhofer AISEC and Graz University of Technology have developed a new tool for software security testing. The tool automatically detects those lines of code that reveal secret information to other programs when executed on modern processors. These information leaks leave treacherous traces in the processor and open so-called side channels that can be tapped by malware. This can then be used to reconstruct secrets that endanger the security of the entire system.
Projects of security evaluation and the development of security solutions are confidential. Their reference on this website is subject to the prior approval of the industrial partner.