Bavarian Chip Design Center

Bavaria on course to become a center of innovation and excellence in chip design

Press release /

© Fraunhofer IIS/Paul Pulkert
From left to right: Dr. Thorsten Edelhäußer (Fraunhofer IIS), Prof. Dr. Ralph Schneider (OTH Regensburg), Prof. Dr. Niels Oberbeck (TH Nürnberg), Prof. Dr. Kathrin Möslein (FAU Erlangen-Nürnberg), Prof. Dr. Georg Sigl (Fraunhofer AISEC), Bavaria's Minister of Economic Affairs Hubert Aiwanger, Prof. Dr. Alexander Martin (Fraunhofer IIS), Prof. Dr. Christoph Kutter (Fraunhofer EMFT)

On January 18, 2024, the Bavarian Chip Design Center (BCDC) reached an important milestone on its path toward making Bavaria a leading location for innovation and excellence in chip design. As part of the Symposium on Chip Development – Greater Innovation through Chip Design, held at Fraunhofer IIS, Bavaria’s Minister of Economic Affairs Hubert Aiwanger presented the Center with a grant of 50 million euros.

The BCDC has set itself the ambitious goal of further expanding chip design expertise in Bavaria and providing companies, especially start-ups and small and medium-sized enterprises (SMEs), with easier access to chip design and suitable supply chains. The recent challenges in German industry have once again highlighted the sector’s dependence on international semiconductor companies and underscore the importance of having a strong chip design center.

“Chip design holds strategic significance: those who help develop the semiconductors of tomorrow secure their own influence on the global market. That is precisely our goal for Bavaria. In addition, there is considerably more added value in designing the chips than in actually manufacturing them. Our semiconductor policy is therefore putting the focus on the right areas. With its three participating institutes, the Fraunhofer-Gesellschaft is the right partner for this project. We in the state government already paved the way for the Bavarian Chip Design Center in previous years with our own semiconductor initiatives. With this additional 50 million, we’re making a clear commitment to the semiconductor industry in Bavaria,” says Hubert Aiwanger, State Minister of Economic Affairs, Regional Development and Energy.

The funding approval marks a milestone in the development of the BCDC, which was launched in 2022 with an initial grant of one million euros. Since 2022, the Fraunhofer Institutes for Applied and Integrated Security AISEC, for Electronic Microsystems and Solid State Technologies EMFT, and for Integrated Circuits IIS have been driving research, identifying key topics, and developing concepts to qualify more specialists for integrated circuit (IC) design and provide access to IC production and supply chains. They also seek to establish access to an IC design ecosystem that makes it easier for SMEs and start-ups to break into IC development.


BCDC: A competence center for chip design

With the second grant from the Bavarian Ministry of Economic Affairs, Regional Development and Energy, the BCDC can further expand its research expertise and, together with five Bavarian colleges and universities as partners, develop into a leading competence center for chip design in the state.

The Bavarian Chip Design Center is organized into three pillars, each focused on a core topic:

  • The IC – Design Ecosystem pillar features platforms that support the development of specific solutions in the areas of sensor/actuator systems and AI, digital signal processing, secure systems-on-chip, and chiplets. This pillar also develops IP portfolios for innovative and novel technologies and explores solutions to minimize the risk of obsolescence and chip shortages.
  • The IC – Design Talents pillar addresses the shortage of skilled workers in chip design through on-the-job training for suitable talent.
  • The IC – Supply Chain pillar helps companies in the production of their own integrated circuits as prototypes and small batches.

In addition to expanding research capacity, efforts are underway to establish a network with industry and promote strategic initiatives at both the national and EU levels. The Bavarian Ministry of Economic Affairs, Regional Development and Energy is supporting the co-financing of a planned German pilot line submitted by the Research Fab Microelectronics Germany (FMD) as part of the European Chips Act through a dedicated part of the project.

As part of the five-year funded project, the partners have been entrusted with meeting the challenges of chip development and production through expertise, innovative strength, and networking. This is how the BCDC will play a key role in advancing the technological sovereignty and competitiveness of the Bavarian economy. 


Security technologies based on open RISC-V designs

Fraunhofer AISEC contributes its scientific expertise in the design, development and testing of secure systems to the Bavarian Chip Design Center. The researchers develop new security technologies for trusted electronics and hardened processors based on open RISC-V designs. Through close integration with the hardware, new operating system components enable secured software environments based on isolation mechanisms such as Trusted Execution Environments and Confidential Computing. In addition, verified boot processes, secure firmware updates and architecture-based HW/SW countermeasures provide protection against commonly exploited software vulnerabilities.

"Microcontrollers and processors can be found in almost all electronic devices and systems, from computers and laptops to industrial equipment and IoT devices. The Bavarian Chip Design Center adds to the knowledge about trusted microchip design. The goal is to reduce entry barriers to individually tailored microelectronics, particularly for small and medium-sized companies, using the developed technology platform, in order to strengthen the competitiveness and technological sovereignty of the Bavarian, German, and European economies. Fraunhofer AISEC develops customized security functions based on the open hardware standard RISC-V," explains Prof. Dr. Georg Sigl, Director at Fraunhofer AISEC.